1. Field of the Invention
The present invention relates to test and measurement systems, and more particularly to systems and methods for generating waveforms.
2. Description of Related Art
Arbitrary waveform generators (ARBs) are waveform generators that are capable of generating any arbitrary signal within the bandwidth of the generator. ARBs store digital descriptions of a signal in digital memory and play them out as analog signals. The digital descriptions are samples of data that are converted to analog signals using a digital-to-analog converter.
The amount of signal that can be stored in the memory space in a typical ARB is limited. For example, storing 10 G samples in a typical ARB generates only about 8 seconds of playtime. ARBs may include a sequencer to make more efficient use of the memory by playing the waveform repetitively in a loop.
Some ARBs use complex sequencers to control the playing of the waveform. Complex sequencers allow for waveforms to be played in nested loops to generate more sophisticated waveforms. One part of a signal may be a waveform stored in one part of memory to be played out in one loop, and another part of the signal may be a different waveform played out in a second loop nested in the first loop. When the nested loops are run by the sequencer, the varying output signal is generated as the combination of the waveforms.
The varying output signals are often produced in response to an externally applied trigger signal. It is desirable to have the output signal appear as soon as possible after the trigger is applied. However, the repeatability of this output latency for repeated trigger inputs is often more important than the latency itself.
To reduce the cost of memory and other digital electronics, most ARBs process the digital waveform data at a sub-multiple of the output sample rate. In many cases, the input trigger is latched with this lower speed clock. This gives rise to a larger output latency uncertainty, depending on when the trigger is received in relation to the lower rate clock.
Sequencers are typically implemented using programmable logic devices such as field programmable gate arrays (FPGAs). The FPGAs may employ a digital clock manager (DCM), which requires an uninterrupted clock signal. Since the trigger processing is performed in the FPGA at a lower clock rates, there is a relatively large uncertainty in when the trigger arrives. For example, a typical high-speed ARB might have a clock rate of 622 MHz. This is divided down (by 4) to 156 MHz for the main fabric of the FPGA. Hence, there is a trigger uncertainty of 1 FPGA clock period (6.4 ns) as to exactly when a trigger arrives before it is latched by the FPGA clock. With a complex sequencer, there are many actions that can be taken upon detection of a trigger, such as for example, starting a waveform or jumping to a new waveform.
One way to reduce the trigger uncertainty is to use a synchronous trigger. In the synchronous case, the trigger need only arrive some time during the FPGA clock period to achieve the desired triggered waveform. The user must be able to produce the synchronous trigger some time during the 6.4 ns window—with the expectation that the trigger will be acted upon on the next FPGA rising clock edge. Trigger uncertainties on the order of 1 ps (or less) can be achieved in this way. However many users cannot produce a synchronous trigger (which requires knowledge of the FPGA clock frequency and phase in the trigger generation circuitry. The user is also left with the relatively coarse granularity (6.4 ns) of the FPGA clock in setting when he wants the trigger to occur. Thus if the user is unable to employ the synchronous trigger, they are left with the relatively large FPGA clock (6.4 ns) uncertainty inherent with an asynchronous trigger.
Another way to reduce the asynchronous trigger uncertainty is to gate the sample clock. The sample clock (and FPGA clock) are disabled (gated) and the FPGA clock divider is reset. The waveform data is loaded into the FPGA. Using external high-speed logic (typically ECL) the clocks are gated on with a resolution of one Sample clock (1.6 ns in the case of a 622 MS/s DAC) and the predetermined waveform begins spooling out. This approach has the advantage of greatly reduced trigger latency uncertainty (4 times smaller, in this example) but suffers from several problems. First it can only be used to play a single waveform. Complex sequencing is not supported. Second more expensive and complex latch circuitry at the full sample rate is required. Finally, sequencer architectures that use complex FPGAs with DCMs do not support clock gating. Hence many of the features these FPGAs provide including advanced sequencing, reprogram ability, and smaller size without the time and expense of ASIC development are lost if clock gating is required.
There is a need for methods and systems for obtaining improved asynchronous timing resolution.